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?2002 fairchild semiconductor corporation may 2002 rev. a HUFA76413DK8 HUFA76413DK8 n-channel logic level ultrafet ? power mosfet 60v, 4.8a, 56m ? general description these n-channel power mosfets are manufactured us- ing the innovative ultrafet ? process. this advanced pro- cess technology achieves the lowest possible on- resistance per silicon area, resulting in outstanding perfor- mance. this device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low re- verse recovery time and stored charge. it was designed for use in applications where power efficiency is important, such as switching regulators, switching convertors, motor drivers, relay drivers, low-voltage bus switches, and power management in portable and battery-operated products. applications motor and load control powertrain management features 150c maximum junction temperature uis capability (single pulse and repetitive pulse) ultra-low on-resistance r ds(on) =0.049 ?, v gs = 10v ultra-low on-resistance r ds(on) =0.056 ?, v gs = 5v mosfet maximum ratings t a = 25c unless otherwise noted thermal characteristics this product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. for a copy of the requirements, see aec q101 at: http://www.aecouncil.com/ reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html. all fairchild semiconductor products are manufactured, a ssembled and tested under iso9000 and qs9000 quality systems certification. symbol parameter ratings units v dss drain to source voltage 60 v v gs gate to source voltage 16 v i d drain current 5.1 a continuous (t c =25 o c, v gs =10v) continuous (t c =25 o c, v gs =5v) 4.8 a continuous (t c =125 o c, v gs =5v,r ja =228 o c/w) 1 a pulsed figure 4 a e as single pulse avalanche energy (note 1) 260 mj p d power dissipation 2.5 w derate above 25 o c0.02w/ o c t j ,t stg operating and storage temperature -55 to 150 o c r ja thermal resistance junction to ambient so-8 (note 2) 50 o c/w r ja thermal resistance junction to ambient so-8 (note 3) 191 o c/w r ja thermal resistance junction to ambient so-8 (note 4) 228 o c/w g1 (2) d1 (8) s1 (1) d1 (7) d2 (6) d2 (5) s2 (3) g2 (4) so-8 1
?2002 fairchild semiconductor corporation rev. a HUFA76413DK8 package marking and ordering information electrical characteristics t a = 25c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics (v gs =5v) drain-source diode characteristics notes: 1: starting t j =25c,l=20mh,i as =5.1a 2: r ja is 50 o c/w when mounted on a 0.5 in 2 copper pad on fr-4 at 1 second. 3: r ja is 191 o c/w when mounted on a 0.027 in 2 copper pad on fr-4 at 1000 seconds. 4: r ja is 228 o c/w when mounted on a 0.006 in 2 copper pad on fr-4 at 1000 seconds. device marking device package reel size tape width quantity 76413dk8 HUFA76413DK8t so-8 330mm 12mm 2500 units 76413dk8 HUFA76413DK8 so-8 tube n/a 98 units symbol parameter test conditions min typ max units b vdss drain to source breakdown voltage i d =250 a, v gs =0v 60 - - v i dss zero gate voltage drain current v ds =50v - - 1 a v gs =0v t a =150 o c- - 250 i gss gate to source leakage current v gs = 16v - - 100 na v gs(th) gate to source threshold voltage v gs =v ds ,i d =250 a1-3v r ds(on) draintosourceonresistance i d =5.1a,v gs = 10v - 0.041 0.049 ? i d =4.8a,v gs = 5v - 0.048 0.056 i d =4.8a,v gs =5v t a =150 o c - 0.091 0.106 c iss input capacitance v ds =25v,v gs =0v, f=1mhz -620- pf c oss output capacitance - 180 - pf c rss reverse transfer capacitance - 30 - pf q g(tot) total gate charge at 10v v gs =0vto10v v dd =30v i d =4.8a i g =1.0ma 18 23 nc q g(5) total gate charge at 5v v gs = 0v to 5v - 10 13 nc q g(th) threshold gate charge v gs = 0v to 1v - 0.6 0.8 nc q gs gate to source gate charge - 1.8 - nc q gd gate to drain ?miller? charge - 5 - nc t on turn-on time v dd =30v,i d =1a v gs =5v,r gs =16 ? --44ns t d(on) turn-on delay time - 10 - ns t r rise time - 19 - ns t d(off) turn-off delay time - 45 - ns t f fall time - 27 - ns t off turn-off time - - 108 ns v sd source to drain diode voltage i sd = 4.8a - - 1.25 v i sd = 2.4a - - 1.0 v t rr reverse recovery time i sd =4.8a,di sd /dt = 100a/ s- - 43 ns q rr reverse recovered charge i sd =4.8a,di sd /dt = 100a/ s- - 55 nc
?2002 fairchild semiconductor corporation rev. a HUFA76413DK8 typical characteristics t a = 25c unless otherwise noted figure 1. normalized power dissipation vs ambient temperature figure 2. maximum continuous drain current vs case temperature figure 3. normalized maximum transient thermal impedance figure 4. peak current capability t a , ambient temperature ( o c) power dissipation multiplier 0 0255075100 150 0.2 0.4 0.6 0.8 1.0 1.2 125 0 2 4 6 25 50 75 100 125 150 -i d , drain current (a) t a , case temperature ( o c) v gs = 10v, r ja =50 o c/w v gs =5v,r ja =228 o c/w 0.001 0.01 0.1 1 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 4 10 -5 t , rectangular pulse duration (s) z ja , normalized thermal impedance notes: duty factor: d = t 1 /t 2 peak t j =p dm xz ja xr ja +t a p dm t 1 t 2 0.5 0.2 0.1 0.05 0.01 0.02 duty cycle - descending order single pulse v gs =10v r ja =50 o c/w 10 100 300 2 10 -5 10 -3 10 -4 10 -2 10 -1 10 0 10 1 10 2 10 3 i dm , peak current (a) t, pulse width (s) transconductance may limit current in this region v gs =5v t a =25 o c i=i 25 175 - t a 150 for temperatures above 25 o c derate peak current as follows: v gs =10v r ja =50 o c/w
?2002 fairchild semiconductor corporation rev. a HUFA76413DK8 figure 5. forward bias safe operating area figure 6. unclamped inductive switching capability figure 7. transfer characteristics figure 8. saturation characteristics figure9. draintosourceonresistancevsgate voltage and drain current figure 10. normalized drain to source on resistance vs junction temperature typical characteristics t a = 25c unless otherwise noted 1 10 100 110100 0.2 200 v ds , drain to source voltage (v) i d , drain current (a) t j = max rated t a =25 o c single pulse limited by r ds(on) area may be operationinthis 100 s 10ms 1ms 1 10 0.1 1 10 15 40 i as , avalanche current (a) t av , time in avalanche (ms) starting t j =25 o c starting t j = 150 o c t av = (l)(i as )/(1.3*rated bv dss -v dd ) if r = 0 if r 0 t av = (l/r)ln[(i as *r)/(1.3*rated bv dss -v dd )+1] 0 5 10 15 20 25 1.5 2.0 2.5 3.0 3.5 4.0 i d , drain current (a) v gs , gate to source voltage (v) pulse duration = 80 s duty cycle = 0.5% max v dd = 15v t j =150 o c t j =25 o c t j =-55 o c 0 5 10 15 20 25 0 0.5 1.0 1.5 2.0 i d , drain current (a) v ds , drain to source voltage (v) v gs =3.5v pulse duration = 80 s duty cycle = 0.5% max v gs =3v t a =25 o c v gs =5v v gs = 10v 40 50 60 70 80 90 100 246810 i d =1a v gs , gate to source voltage (v) i d =5.1a r ds(on) , drain to source on resistance (m ? ) pulse duration = 80 s duty cycle = 0.5% max 0.5 1.0 1.5 2.0 -80 -40 0 40 80 120 160 normalized drain to source t j , junction temperature ( o c) on resistance v gs = 10v, i d =5.1a pulse duration = 80 s duty cycle = 0.5% max
?2002 fairchild semiconductor corporation rev. a HUFA76413DK8 figure 11. normalized gate threshold voltage vs junction temperature figure 12. normalized drain to source breakdown voltage vs junction temperature figure 13. capacitance vs drain to source voltage figure 14. gate charge waveforms for constant gate currents figure 15. switching time vs gate resistance typical characteristics t a = 25c unless otherwise noted 0.6 0.8 1.0 1.2 -80 -40 0 40 80 120 160 normalized gate t j , junction temperature ( o c) v gs =v ds ,i d = 250 a threshold voltage 0.9 1.0 1.1 1.2 -80 -40 0 40 80 120 160 t j , junction temperature ( o c) normalized drain to source i d = 250 a breakdown voltage 10 100 1000 0.1 1 10 60 2000 c, capacitance (pf) v ds , drain to source voltage (v) v gs =0v,f=1mhz c iss = c gs +c gd c oss ? c ds +c gd c rss = c gd 0 2 4 6 8 10 0 5 10 15 20 v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 30v i d =4.8a i d =1a waveforms in descending order: 0 50 100 150 0 1020304050 switching time (ns) r gs , gate to source resistance ( ? ) v gs =5v,v dd =30v, i d =1a t d(off) t r t d(on) t f
?2002 fairchild semiconductor corporation rev. a HUFA76413DK8 test circuits and waveforms figure 16. unclamped energy test circuit figure 17. unclamped energy waveforms figure 18. gate charge test circuit figure 19. gate charge waveforms figure 20. switching time test circuit figure 21. switching time waveforms t p v gs 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 r l v gs + - v ds v dd dut i g(ref) v dd q g(th) v gs =1v q g(5) v gs =5v q g(tot) v gs = 10v v ds v gs i g(ref) 0 0 q gs q gd v gs r l r gs dut + - v dd v ds v gs t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0
?2002 fairchild semiconductor corporation rev. a HUFA76413DK8 thermal resistance vs. mounting pad area the maximum rated junction temperature, t jm ,andthe thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, p dm ,inan application. therefore the application?s ambient temperature, t a ( o c), and thermal resistance r ja ( o c/w) must be reviewed to ensure that t jm is never exceeded. equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. in using surface mount devices such as the so-8 package, the environment in which it is applied will have a significant influence on the part?s current and maximum power dissipation ratings. precise determination of p dm is complex and influenced by many factors: 1. mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. the number of copper layers and the thickness of the board. 3. the use of external heat sinks. 4. the use of thermal vias. 5. air flow and board orientation. 6. for non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. fairchild provides thermal information to assist the designer?s preliminary application evaluation. figure 22 defines the r ja for the device as a function of the top copper (component side) area. this is for a horizontally positioned fr-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. this graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. pulse applications can be evaluated using the fairchild device spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. thermal resistances corresponding to other copper areas canbeobtainedfromfigure22orbycalculationusing equation 2. the area, in square inches is the top copper area including the gate and source pads. the dual die so-8 package introduces an additional thermal coupling resistance, r b. equation 3 describes r b as a function of the top copper mouting pad area. the thermal coupling resistance vs. copper area is also graphically depicted in figure 22. (eq. 1) p dm t jm t a ? () r ja ----------------------------- = (eq. 2) r ja 103.2 24.3 area () ln ? = (eq. 3) r b 46.4 21.7 area () ln ? = figure 22. thermal resistance vs mounting pad area 0 50 100 150 200 250 300 0.001 0.01 0.1 1 r ? ,r ja ( o c/w) area, top copper area (in 2 ) per die 191 o c/w - 0.027in 2 228 o c/w - 0.006in 2 r ja = 103.2 - 24.3 * ln (area) r ? = 46.4 - 21.7 * ln (area)
?2002 fairchild semiconductor corporation rev. a HUFA76413DK8 pspice electrical model .subcktHUFA76413DK8t213; revapril2002 ca 12 8 7.8e-10 cb 15 14 9.8e-10 cin 6 8 5.8e-10 dbody 7 5 dbodymod dbreak 5 11 dbreakmod dplcap 10 5 dplcapmod ebreak11717 1867.4 eds148581 egs138681 esg 6 10 6 8 1 evthres 6 21 19 8 1 evtemp20618221 it8171 ldrain 2 5 1e-9 lgate 1 9 1.34e-9 lsource 3 7 0.59e-9 mmed16688mmedmod mstro16688mstromod mweak162188mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 22.5e-3 rgate 9 20 2.2 rldrain 2 5 10 rlgate1913.4 rlsource 3 7 5.9 rslc1551rslcmod1e-6 rslc25501e3 rsource 8 7 rsourcemod 15.3e-3 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b1312138s1bmod s2a 6 15 14 13 s2amod s2b13151413s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51)/abs(v(5,51)))*(pwr(v(5,51)/(1e-6*180),2.5))} .model dbodymod d (is = 8e-13 rs = 1.58e-2 trs1 = 1e-3 trs2 = 3e-6 xti=3.2 cjo = 8e-10 tt = 3.2e-8 m = 0.54) .model dbreakmod d (rs = 1.18 trs1 = 2e-3 trs2 = -2.6e-5) .model dplcapmod d (cjo = 5.7e-10 is = 1e-30 n = 10 m = 0.87) .modelmmedmodnmos(vto=1.68kp=2is=1e-30n=10tox=1l=1uw=1urg=2.2) .model mstromod nmos (vto = 2.05 kp =35 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model mweakmod nmos (vto = 1.48 kp = 0.04 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 22 rs = 0.1) .model rbreakmod res (tc1 = 1.15e-3 tc2 = -7.5e-7) .model rdrainmod res (tc1 = 8.5e-3 tc2 = 1.2e-5) .model rslcmod res (tc1 = 3e-2 tc2 = 5.3e-7) .model rsourcemod res (tc1 = 1e-3 tc2 = 1e-6) .model rvthresmod res (tc1 = -1.4e-3 tc2 = -7e-6) .model rvtempmod res (tc1 = -1.5e-3 tc2 = 2e-7) .model s1amod vswitch (ron = 1e-5 roff = 0.1 von = -5.0 voff= -1.0) .model s1bmod vswitch (ron = 1e-5 roff = 0.1 von = -1.0 voff= -5.0) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = -0.2 voff= 0.2) .model s2bmod vswitch (ron = 1e-5 roff = 0.1 von = 0.2 voff= -0.2) .ends note: for further discussion of the pspice model, consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; ieee power electronics specialist conference records, 1991, written by william j. hepp and c. frank wheatley. 18 22 + - 6 8 + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6
?2002 fairchild semiconductor corporation rev. a HUFA76413DK8 saber electrical model rev april 2002 template HUFA76413DK8t n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 8e-13, rs = 1.58e-2, trs1 = 1e-3, trs2 = 3e-6, xti = 3.2, cjo = 8e-10, tt = 3.2e-8, m = 0.54) dp..model dbreakmod = (rs = 1.18, trs1 = 2e-3, trs2 = -2.6e-5) dp..model dplcapmod = (cjo = 5.7e-10, isl =10e-30, nl =10, m = 0.87) m..model mmedmod = (type=_n, vto = 1.68, kp = 2, is =1e-30, tox=1) m..model mstrongmod = (type=_n, vto = 2.05, kp = 35, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.48, kp = 0.04, is = 1e-30, tox = 1, rs=0.1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.0, voff = -1.0) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1.0, voff = -5.0) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.2, voff = 0.2) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.2) c.ca n12 n8 = 7.8e-10 c.cb n15 n14 = 9.8e-10 c.cinn6n8=5.8e-10 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 1.34e-9 l.lsource n3 n7 = 0.59e-9 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 1.15e-3, tc2 = -7.5e-7 res.rdrain n50 n16 = 22.5e-3, tc1 = 8.5e-3, tc2 = 1.2e-5 res.rgate n9 n20 = 2.2 res.rldrainn2n5=10 res.rlgate n1 n9 = 13.4 res.rlsource n3 n7 = 5.9 res.rslc1 n5 n51= 1e-6, tc1 = 3e-2, tc2 =5.3e-7 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 15.3e-3, tc1 = 1e-3, tc2 =1e-6 res.rvtemp n18 n19 = 1, tc1 = -1.5e-3, tc2 = 2e-7 res.rvthres n22 n8 = 1, tc1 = -1.4e-3, tc2 = -7e-6 spe.ebreak n11 n7 n17 n18 = 67.4 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/180))** 2.5)) } } 18 22 + - 6 8 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap iscl rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6
?2002 fairchild semiconductor corporation rev. a HUFA76413DK8 spice thermal model rev april 2002 HUFA76413DK8t copper area = 0.493in 2 ctherm1th88.5e-4 ctherm2871.8e-3 ctherm3765.0e-3 ctherm4651.3e-2 ctherm5544.0e-2 ctherm6431.5e-1 ctherm7327.5e-1 ctherm8 2 tl 3 rtherm1th83.5e-2 rtherm2876.0e-1 rtherm3762 rtherm4658 rtherm55418 rtherm64320 rtherm73223 rtherm8 2 tl 25 saber thermal model saber thermal model HUFA76413DK8t copper area = 0.493in 2 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 =8.5e-4 ctherm.ctherm287=1.8e-3 ctherm.ctherm376=5.0e-3 ctherm.ctherm465=1.3e-2 ctherm.ctherm554=4.0e-2 ctherm.ctherm643=1.5e-1 ctherm.ctherm732=7.5e-1 ctherm.ctherm8 2 tl =3 rtherm.rtherm1 th 8 =3.5e-2 rtherm.rtherm287=6.0e-1 rtherm.rtherm376=2 rtherm.rtherm465=8 rtherm.rtherm554=18 rtherm.rtherm643=20 rtherm.rtherm732=23 rtherm.rtherm8 2 tl =25 } rtherm6 rtherm8 rtherm7 rtherm5 rtherm4 rtherm3 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 tl 2 3 4 5 6 7 junction case 8 th rtherm2 rtherm1 ctherm7 ctherm8
rev. h5 trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. acex? bottomless? coolfet? crossvolt? densetrench? dome? ecospark? e 2 cmos? ensigna? fact? fact quiet series? fast ? fastr? frfet? globaloptoisolator? gto? hisec? i 2 c? isoplanar? littlefet? microfet? micropak? microwire? optologic ? optoplanar? pacman? pop? power247? powertrench ? qfet? qs? qt optoelectronics? quiet series? silent switcher ? smart start? spm? star*power? stealth? supersot?-3 supersot?-6 supersot?-8 syncfet? tinylogic? trutranslation? uhc? ultrafet ? vcx? disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information formative or in design this datasheet contains the design specifications for product development. specifications may change in any manner without notice. preliminary first production this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. no identification needed full production this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. obsolete not in production this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. star*power is used under license

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